Concurrent error detection/correction in the HAL MMU chip
D.C.-W. Chang, N.R. Saxena · 2002
The authors describe three concurrent error detection and correction methods used in various address translation tables in the HAL Memory Management Unit (MMU). Virtually indexed and virtually tagged cache architecture is exploited to provide an almost fault-secure hardware coherence mechanism in MMU. Low overhead linear polynomial codes have been chosen in these designs to minimize both the hardware and software instrumentation impact.