VHDL for FPGA design
G. Olsen, W.O. McDermith · Proceedings of WESCON '93 · 2002
VHDL is a language used to describe digital circuits. It is a powerful language, originally intended for simulation, but is now being applied to synthesis. Descriptions of digital hardware in VHDL can be described in terms of structure, behavior, or a mixture of the two description styles.