A tool converting finite state machine to VHDL
Amr Talaat Abdel-Hamid, Mohamed H. Zaki, Sofiène Tahar · 2004
Finite state machines (FSM) are a basic component in hardware design; they represent the transformation between inputs and outputs for sequential designs. FSMs can be represented graphically, which would help the designer to visualize and design in a more efficient way; on the other hand the designer requires a fast direct way to convert the visualized design to hardware description language (HDL) code directly in order to simulate and implement it for synthesis and analysis. In this paper, we present a tool which, starting from a graphical FSM representation, produces a behavioral HDL code which can be directly analyzed and synthesized.