A STEADY-STATE RESPONSE TEST GENERATION FOR MIXED-SIGNAL INTEGRATED CIRCUITS
A.F. Alani, G. Musgrave, Anthony P. Ambler · 2005
All s t r ac t A new approach to generate test vectors for Mixed-Signal Integrated Circuits (MS1C)s based on time response analysis is presented. The main objective is the development of a fast test generation to detect catastrophic faults in MSICs with keeping test overheads (chip area and pin count) at minimum.