Phantom redundancy: a high-level synthesis approach for manufacturability
Balakrishnan Iyer, Ramesh Karri, Israel Koren · 1995
Phantom redundancy, an area-efficient technique for fabrication-time reconfigurability is presented. Phantom redundancy adds extra interconnect so as to render the resulting microarchitecture reconfigurable in the presence of any (single) functional unit failure. The proposed technique yields partially good chips in addition to perfect chips. A genetic algorithm is used to incorporate phantom redundancy constraints into microarchitecture synthesis. The algorithm minimizes the performance degradation due to any faulty functional unit of the resulting microarchitecture. The effectiveness of the technique is illustrated on benchmark examples. 1 INTRODUCTION A number of researchers have examined fabricationtime reconfiguration approaches to enhance the yield of ICs. Built-In-Self-Repair (BISR) is one approach to fabrication time reconfiguration. In BISR fault tolerance is realized by providing a set of spare modules in addition to the core operational modules[1]. BISR approaches have bee...