Optimized VLIW architecture for non-zero IF QAM-modem implementations
A.K. Pani, R. V. Raja Kumar · 2006
Today's general purpose DSPs keep data memory and instruction memory separate to exploit the advantages of the HARVARD architecture in addition to gaining from the instruction level parallelism available in programs through the VLIW approach. In this paper we propose an architecture, which is optimized for modem (with carrier and symbol synchronization) implementations by making small modifications to a typical VLIW processor architecture. It is being claimed to be optimized since the most hardware intensive multipliers remain busy for almost 100% of the time and data fetches are done parallelly from a fixed locality facilitated by a unit named data pump. In this implementation, an instruction, namely, MMAC, which clubs two multiplications and one addition has been proposed. In addition to this, zero overhead branch instruction also has been included for the processor to be speed optimized in implementing the modem. Performance comparison has been carried out to find almost 8.5X speed enhancement over TMS320C62X and approximately 7X speed enhancement over TMS320C54X machine for modem implementations with carrier and symbol recovery. The superb speeding up is achieved at a cost of a small increase in the hardware (approximately 18750 gates).