Overview of the PIPE processor implementation
Matthew Farrens, Andrew R. Pleszkun · 2002
PIPE (parallel instruction with pipelined execution) processor is a 32-bit pipelined single chip processor with a simplified load-store instruction set, a five stage pipeline, a two-cycle ALU, and the following unique features: architectural queues; delayed branch scheme; sophisticated instruction cache, branch register file; subroutine call support; and branch queues. The nMOS implementation and lessons learned from it are discussed.>