Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms
Andrea Marongiu, Luca Benini, Mahmut Kandemir · 2007
Many MPSoC applications are loop-intensive and amenable to automatic parallelization with suitable compiler support. One of the key components of any compiler-parallelized code is barrier instructions which are used to perform global synchronization across parallel processors. This scenario calls for a lightweight synchronization infrastructure.