Low Power and High Speed Network on Chip Architecture for BP Neural Network
Yiping Dong, Yinghe Li, Yang Wang, Takahiro Watanabe · ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications · 2009
Back Propagation Artificial Neural Network (BP-ANN), one of widely used neural networks, has been used in a lot of areas. Hardware architecture of BP-ANN was proposed by using an NoC (Network on Chip) and implemented on FPGA. In this paper, new NoC architecture which has a torus topology and IXY (Intelligent XY) routing algorithm is developed for BP-ANN to make it low power and high performance. This system is implemented by FPGA to estimate system performance and power consumption. NIRGAM NoC simulator is also used to evaluate latency and throughput of this system. Experimental results show that our proposed architecture can increase Connection Per Second (CPS) about 2 times than existing digital hardware ANN; it can reduce communication load which total packet size can reduce about 3.2 times compared with traditional packet transmit method of BP-ANN. It can reduce latency by 23.7% and dynamic power consumption by 7.2% compare with the former NoC architecture BP-ANN. It is reconfigurable and expandable to meet various ANN applications. Furthermore other type ANNs can also be implemented in the system by adjusting a routing algorithm of NoCs.