4-valued BiCMOS circuits for the transmission system of a massively parallel architecture
Daniel Etiemble, Christophe Chanussot, Vincent Néri · 2002
Two versions of four-valued encoder and decoder circuits using a BiCMOS technology are presented. A comparison is made of the performance of CMOS-only and BiCMOS versions of these circuits. Such circuits are intended for use in a four-valued transmission system in the 3D interconnection network of a massively parallel architecture. The main difference in performance between the two versions comes from the use of BiCMOS encoder circuits. As expected, the bipolar transistor that is used gives a significant reduction in chip area (from 20500 lambda /sup 2/ to 11300 lambda /sup 2/). For the entire transmission path, the BiCMOS version has an equivalent propagation delay for the evaluation phase and an improved delay for the precharge phase (3.8 ns instead of 13.2 ns). The total active chip area is reduced by 28%. The advantage of the BiCMOS encoder circuit comes from the decoupling of the process of generation of the four different levels realized by the MOS transistors and that of driving the high-capacitance load. BiCMOS technologies give new circuitry perspectives for four-valued off-chip transmission.>