On test pattern compaction using random pattern fault simulation
Seiji Kajihara, Kewal K. Saluja · 2002
Random pattern fault simulation is known to be an efficient method for accelerating test generation process but it is not suited for generating compact test sets because a test set generated by random pattern fault simulation contains many redundant test vectors. In this paper through a set of experiments we first demonstrate the inverse influence of the initial test set size on the final test set size obtained after compaction. We then propose a novel method of deriving compact test sets based on the random pattern fault simulation and compact test generation already proposed. Experimental results show that for the benchmark circuits our method produces minimum or near minimum test sets in substantially less run time than the methods that do not make use of random vectors.