A new bit-serial architecture of rank-order filter
Takuya Yamamoto, Vasily G. Moshnyaga · 2009
This paper presents a new architecture of rank-order median filter. The architecture processes all window samples in parallel in the bit-serial manner. Unlike related architectures, it neither sorts/swaps nor modifies the window samples and requires less hardware resources. To process k samples, each of N-bits in size, the architecture uses N shift registers of k bits each and a simple logic. It produces the result in N+1 clock cycles independently to the window size.