A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip
TAKAO K. WATANABE, R. Fujita, Kazumasa Yanagisawa, H. Tanaka, Kazushige Ayukawa, M. Soga, Y. Tanaka, Y. Sugie, Y. Nakagome · IEEE Journal of Solid-State Circuits · 1997
A modular architecture for a DRAM-integrated, multimedia chip with a data transfer rate of 6 to 12 Gbyte/s is proposed. The architecture offers the design flexibility in terms of both DRAM capacity and the logic-memory interface for use in a wide variety of applications. A DRAM macro built from cascadable DRAM bank modules having a 256-kb memory capacity and 128-b I/Os provides flexibility and reconfigurability of DRAM capacity and a high data transfer rate with an area of 6.4 mm/sup 2//Mb. A data transfer circuit (called the "reconfigurable data I/O attachment"), which is attached to the I/O lines of the DRAM macro, provides a flexible logic-memory interface by changing the data-transfer routes between the DRAM macro and logic circuits in real time. A 6.4-Gbyte/s test chip (called the "media chip") for three-dimensional computer graphics was fabricated to test the proposed design methodology. It integrates an 8-Mb DRAM and four pixel processors on an 8.35/spl times/14.6-mm chip by using a 0.4-/spl mu/m CMOS design rule.