Feasibility study of designing TSC sequential circuits with 100% fault coverage
S.J. Piestrak · 2003
Several design methods of self-checking synchronous sequential circuits (SMs) have been proposed in the literature. Two principal drawbacks of all these methods are: 1) the internal fault coverage rarely equals to 100% and 2) the checkers used to monitor correct operation of a SM (claimed to be self-testing) contain internal faults which cannot be detected during normal operation by a subset of codewords which, are actually used. In this paper, we analyze the possibility of designing totally self-checking (TSC) SMs protected against errors using unordered codes with 100% fault coverage.