CAM enhanced super parallel SIMD processor with high-speed pattern matching capability
Takeshi Kumaki, Kono Yutaka, Masakatsu Ishizaki, Tagami Masaharu, Tetsushi Koide, Hans Jürgen Mattausch, Takayuki Gyohten, Hideyuki Noda, Yasuto Kuroda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito · Conference proceedings · 2007
A super parallel SIMD processor has been proposed as a novel SIMD multimedia processor, which is better way for processing several types multimedia data. This processor supports 2,048-way bit-serial and word-parallel operation. Moreover, 2,048 Processing elements can synchronize with a single command and process all stored data, thus achieving highly- parallel processing with low power consumption. In this paper, for further improving processing efficiency of multimedia data, a Content Addressable Memory (CAM) is embedded in the super parallel SIMD processor. In case of JPEG application, the original super parallel SIMD processor can reduce the number of average clock cycles about 55% smaller than for the conventional DSP. Furthermore, the clock cycle number with the CAM enhanced super parallel SIMD processor is 90% smaller than with the original super parallel SIMD processor. Thus, the proposed architecture is very suitable for the multimedia data processing.