Efficient encoding for hardware implementation of IRA LDPC on 802.16 standard
Trio Adiono, Agi Prasetiadi, Anugrah Salbiyono · 2010
We propose an encoding scheme for quasi-cyclic low-density parity check (QC-LDPC) suitable for LDPC codes in IEEE 802.16e. We developed accumulated recursive formula to calculate parity bits, so we can encode the message in real time. Basic idea from our method is, use first parity vector recursively to produce another parity vector efficiently. While parity vector is chosen as an output, it also saved in another register for being used in next operation. An encoder architecture is proposed and implemented to verify the results. Later, we discuss the hardware simulation results.