MINT-a VHDL simulation system
Mart Altmäe · European Design Automation Conference · 1990
Several commercial VHDL simulators have been reported. Many of these however only support a subset of the language. This paper describes the development of a Multilevel INTeractive (MINT) simulator that was designed from scratch specifically for VHDL. A brief overview of the complete system is given first. Then generation of executable code for simulation purposes, and some VHDL specific features of the simulation kernel, are described.