Test pattern generators for distributed and embedded built-in self-test at register transfer level
V. Vorisek · 2002
The poster presents Ph.D. thesis in the area of test pattern generators (TPGs) for application in distributed and embedded Built-In Self-Test (BIST). The goal of this work is to develop a general scheme of designing built-in TPGs for basic arithmetic elements such as adders, subtracters, multiplexers, comparators at register transfer level (RTL) of circuit description.