Irreversible bit erasures in binary multipliers
Ismo K. Hänninen, Jarmo Takala, Craig S. Lent · 2011
Nanocircuits will suffer from heat dissipation due to irreversible information erasure, which is a potential new limiting factor for the maximum operating frequencies of the future circuit technologies. This paper estimates the degree of information loss in the binary multiplier structures and demonstrates that the standard hardware approaches are sub-optimal, by several orders of magnitude in comparison with the determined theoretical limit of the multiplication operation. The hardware analysis is based on the arithmetic units proposed for implementation with quantum-dot cellular automata (QCA), a circuit technology reaching molecular device densities and extremely high signal energy conservation. The results are generally applicable to all other emerging technologies based on the majority logic gate.