FPGA Based Implementation of Decoder for Array Low-Density Parity-Check Codes
Pankaj Bhagawat, Momin Uppal, G.S. Choi · 2006
Low density parity check (LDPC) codes have received much attention for their excellent performance, and the inherent parallelism involved in decoding them. We consider a type of structured binary LDPC codes, known as array LDPC codes, which have low encoding complexity and good performance, for implementation on a Xilinx field programmable gate array (FPGA) device.