Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processors
André Seznec, É. Toullec, Olivier Rochecouste · 2002
With the continuous shrinking of transistor size, processor designers are facing new difficulties to achieve high clock frequency. The register file read time, the wake up and selection logic traversal delay and the bypass network transit delay with also their respective power consumptions constitute major difficulties for the design of wide issue superscalar processors.