Partitioning Tradeoffs for Waveform Relaxation in Transient Analysis Circuit Simulation
L. Peterson, Sven Mattisson · 2005
In this paper we present a study of static circuit partitioning algorithms for waveform relaxation used for circuit simulation on a multicomputer. We investigate the important tradeoff between the irregularity of the partitioning and the achievable parallelism. Also, the importance of the accuracy in certain steps in the partitioning calculation has been studied. Purely topological methods are compared with methods that try to quantitatively estimate the convergence factor of the WR iterations. For digital CMOS circuits we find that only the close neighborhood of a circuit node (nearest neighbors) influences the value of the worst-case coupling. The conductive coupling is the essential part to take into account for the partitioning. For a few circuits (mostly circuits with cross-coupling) the capacitive coupling must also be included in the partitioning. It is, however, hard to find an exact limit for the convergence factor estimate.