SDRAM Delay Fault Modeling and Performance Testing
Yu-Tsao Hsing, Chün-chieh Huang, Jen-Chieh Yeh, Cheng‐Wen Wu · Proceedings - IEEE VLSI Test Symposium/Proceedings of the ... IEEE VLSI Test Symposium · 2007
DRAM timing parameter testing has always been considered a time-consuming process. This paper presents a systematic approach to analysis and classification of the synchronous DRAM (SDRAM) delay failure modes. Four delay fault models with March expression are proposed to cover important DRAM timing parameters. By at-speed March testing of these four types of delay faults, the authors can verify the DRAM timing specifications.