BIST hardware generator for mixed test scheme
Christian Dufaza, H. Viallon, Claudine Chevalier · 1995
outputs during test mode which renders internal nodes totally controllable and observable. Thus, test patterns can be scanned in to exercise the internal nodes and response patterns are scanned out for comparison. A better solution would be to use the memory elements, combined with some additional logic, as a Test Pattern Generator (TPG) so as to produce the test patterns inside the circuit itself. Response analysis would also be done on-chip by an Output Response Analyzer (ORA) so as to produce a “PASS/FAIL ” signal. This last technique referred to Built-In Self-Test (BIST) [Wil83], see Figure 1, is regarded today as the solution for tomorrow’s test problems as, owing to the increasing complexity and density of the circuits, testing can be effectively carried out only by dedicating part of the circuit