An 8*8 discrete cosine transform model using VHDL
W. Chen, Yu‐Cheng Fan, Kenneth W. Hsu · 2003
VHSIC hardware description language (VHDL) models are used to simulate a two-dimensional 8*8 discrete cosine transform (DCT) chip. Models are created and simulated in two levels: a behavioral model and a structural model. The whole system is verified by Mentor Graphics VHDL and constructed in true single phase clock (TSPC) logic.>