A Bit Scalable Architecture for Fuzzy Processors with Three Inputs and a Flexible Fuzzification Unit
Roberto d’Amore · Symposium on Integrated Circuits and Systems Design · 2000
This paper describes an architecture of a three input one output bit scalable fuzzy processor. The synthesis is made from a VHDL description. The data path and functional units dimension are defined by a small number of parameters in the highest level entity. The knowledge base and the membership functions are stored in distinct units in the circuit description for an easy control strategy modification.