An approach to fast hierarchical fault simulation
Akira Motohara, M Murakami, Miki Urano, Yasuo Masuda, Masahide Sugano · Design Automation Conference · 1988
The authors present an approach to hierarchical fault simulation which generates several simulation models of one circuit and carries out simulation for each. Fault insertion and simulation-model generation is done automatically. Switch-level simulation which utilizes lookup tables is as fast as gate-level simulation. Experimental results show that using behavioral description and switch-level truth tables is effective in improving simulation speed. >