Design of a fully-pipelined systolic array for flexible transposition-free VLSI of 2-D DFT
Pramod Kumar Meher · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 2005
A novel approach to design an efficient systolic structure to implement the two-dimensional discrete Fourier transform (DFT) is presented. The proposed systolic structure consists of (N/spl times/N) simple locally connected processing elements that perform two complex multiplications and two additions during a cycle period. It does not involve any transposition operation and, therefore, the corresponding hardware and time is saved by the structure. It offers full pipelining, and computes a two-dimensional DFT of size (N/spl times/N) in every N cycles without interruption, since the first stage of operations for one input array may be performed concurrently with second stage of operations of its preceding input array.