Verification of high level synthesis designs through gate level simulation of compiled module implementations
Thomas E. Fuhrman, Donald E. Thomas, Rajeev Murgai, E. Un · 2002
The evaluation of a high-level synthesis system is described. The output of the synthesis system is translated automatically to the input of a commercially available silicon compiler, and the output of the silicon compiler is simulated to determine functional and timing correctness of an experimental design. Results show that a correct design is produced.>