On integrating a proprietary and a commercial architecture for optimal BIST performances in SoCs
Alfredo Benso, Stefano Di Carlo, Silvia Chiusano, P. Prinetto, F. Ricciato, M. Lobetti Bodoni, M. Spadari · 2002
This paper presents the integration of a proprietary hierarchical and distributed test access mechanism called HD/sup 2/BIST and a BIST insertion commercial tool. The paper briefly describes the architecture and the features of both the environments and it presents some experimental results obtained on an industrial SoC.