A 25 MHz 5*7 spatial filter chip for realtime image processing
Toru Kawata, J. Son, N. Tomari, Kohei Yamauchi, N. Miyakawa, K. Sasuga, K. Taniuchi · 2002
A 25 MHz 5*7 spatial filter chip has been developed using CMOS 2 mu m process for realtime image processing. The filtering coefficients are specified in a 12-bit floating-point format for higher precision arithmetic. Each multiplier has three coefficient registers for changing the coefficient values in realtime. It contains about 71000 transistors on a 11.7*13.3 mm/sup 2/ die.>