622 Mb/s 8×8 shared multibuffer ATM switch with hierarchical queueing and multicast functions
H. Yamanaka, Hideo Saitô, Hiroaki Yamada, M. Tsuzuki, S. Kohama, Hiromi H. Ueda, Harufusa Kondoh, Yoshio Matsuda, K. Oshima · 2002
A new ATM switch architecture, named the shared multibuffer architecture, features great advantages in the access speed, overall size of the buffer memories, and the cell loss performance. We have developed a 622 Mb/s 8/spl times/8 shared multibuffer ATM switch with multicast and hierarchical queueing functions to accommodate 156 Mb/s, 622 Mb/s and 2.4 Gb/s interfaces. Implementation of the shared multibuffer ATM switch is described with respect to four sorts of 0.8-/spl mu/m BiCMOS LSIs and an ATM switch board. The switch board consists of four aligner-LSIs, nine buffer-LSIs and one control-LSI (or control/type 2-LSI). Possible applications to an ATM access system and a 2.4 Gb/s ATM loop system are also discussed.>