Dynamic test sequence compaction for sequential circuits
Anand Raghunathan, Srimat Chakradhar · 2002
This work addresses two important issues in dynamic test sequence compaction for sequential circuits: (1) extension of partially specified test sequence to detect other faults, and (2) reduction in the number of secondary faults that have to be considered while extending partially specified test sequence. We present a sliding anchor frame technique to specify unspecified signal in a test sequence. Key features of the sliding anchor frame technique are: (1) test generator deterministically assigns logic values to unspecified signals rather then randomly specified signals as 0 or 1, and (2) every vector in the partially specified test sequence is considered as an anchor vector during the extension of the sequence. This effectively shows observation of fault effects at any vector in the sequence, which is essential for obtaining test sets of high quality. Experimental results on several sequential circuits show that the sliding anchor frame technique results in significant reductions in test set size end test application cycles.