An efficient architecture of encoder and decoder for DisplayPort physical layer
Yongtae Kim, Junyoung Song, Woonhyung Heo, Chulwoo Kim · 2009
This paper presents an efficient architecture of encoder and decoder for DisplayPort. The proposed architecture provides high-speed and low-complexity for the hardware specified by the DisplayPort standard. Moreover, the encoder and decoder require gate counts of only 0.94K and 0.89K, respectively.