A 4-Bits CSA Adder Using the Arithmetic A2 Redundant Binary Representation for Mixed Neural Networks with On-Chip Learning
Hatem Boukadida, Zied Gafsi, Néjib Hassen, Kamel Besbes · 2008
This paper presents a time-efficient 4-bits carry select adder (CSA) using the arithmetic A2 redundant binary representation. This structure is very suitable for implementation in VLSI of simple mixed-signal neural networks with on-chip learning. This adder is based on a classical weighted binary carry-select adder with two input/output trans-coders. Comparisons with another FPGA-based A2 adder show that the proposed CMOS structure offers a significant increase in speed, while consuming a little more area.