VLSI video codec using programmable DSP
T. Tajiri, Yutaka Suzuki, Hiroshi Yoshimura · 2003
A video codec based on CCITT's standardized p*64 video coding algorithm and communication protocol has been developed for ISDN H0 rate transmission. The codec is fabricated on two 280-mm*280-mm boards and is composed of new DSPs, four kinds of NTSC-CIF (National Television Committee-Common Intermediate Format) mutual conversion LSIs, a transmission codec LSI, and an AD/DA (analog-to-digital/digital-to-analog) hybrid IC. The codec codes and decodes full CIF signs at a rate of 15 frames/s and communicates at an ISDN 384-kb/s rate. Application programs for the codec, such as picture reconstruction capability driven by DSPs in the coder or decoder, can be performed by using residual DSP processing power without the need for any hardware addition.>