Evaluation of the SPUR Lisp architecture
George S. Taylor, Paul N. Hilfinger, James R. Larus, Dave Patterson, B. Zorn · ACM SIGARCH Computer Architecture News · 1986
The SPUR microprocessor has a 40-bit tagged architecture designed to improve its performance for Lisp programs. Although SPUR includes just a small set of enhancements to the Berkeley RISC-II architecture, simulation results show that with a 150-ns cycle time SPUR will run Common Lisp programs at least as fast as a Symbolies 3600 or a DEC VAX 8600. This paper explains SPUR's instruction set architecture and provides measurements of how certain components of the architecture perform.