Unrestricted faithful rounding is good enough for some LNS applications
Mark G. Arnold, Colin D. Walter · 2002
We propose to relax the restricted form of faithful rounding used in prior 32 bit logarithmic number system (LNS) implementations. Unrestricted faithful rounding yields three- to six-fold savings in VLSI ROM size (or four- to six-fold savings in FPGA table size) with only a modest increase in error. This can be acceptable for the DSP and multimedia applications in which the non-standard LNS is a candidate for adoption. Such applications are cost sensitive, and the tremendous cost reduction of the LNS model proposed should argue very favourably for its adoption.