Logic simulation system using simulation processor (SP)
Masaki Saitoh, Kiyoshi Iwata, Akihiro Nakamura, M. Kakegawa, J. Masuda, H. Hamamura, Fumiyasu Hirose, Nobuaki Kawato · Design Automation Conference · 1988
This paper describes a (special-purpose) logic simulation processor (SP) and a software system for the SP for use in verifying the design of computers and other logic devices. Our system can evaluate a logic circuit containing 4 million logic primitives and 32M bytes of memory at a maximum speed of 800 million active primitive evaluations per second.This paper outlines the hardware architecture, then discusses a software system that optimizes hardware performance. It presents the results of system use and evaluates the system.