Architectural exploration and optimization for counter based hardware address generation
M. Miranda, Mathias Kaspar, Francky Catthoor, Hillarie Man · 1997
A set of automated system level techniques is pre# sented for architectural exploration and optimization of counter based address generation units in real time signal processign systems. The goal is to explore di#er# ent architectural alternatives available when mapping array references in order to select the most promising ones in areacost. The techniques are demonstratedon realistic test#vehicles# showing that architectural deci# sion at early stages of the design process# can have a very large impact on the resulting area #gure. 1 Introduction The increasing requirements in throughput for memory intensive signal processing applications and the use of distributed memory architectures to pro# vide enough bandwidth in the memory access# im# pose a tight cycle budget for memory address evalua# tion. Therefore# address manipulation forms a crucial componentofany architecture which deals with data# dominated algorithms. In that case# e#cient access to the memories within real#time cons...