Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading
R.P. Preston, R.W. Badeau, Dan Bailey, Shane Bell, Larry Biro, William J. Bowhill, D.E. Dever, S. Felix, R. Gammack, V. Germini, M.K. Gowan, P.E. Gronowski, D.B. Jackson, Shekhar Mehta, Shannon Morton, J.D. Pickholtz, M.H. Reilly, M.J. Smith · 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 2005
A 250M transistor microprocessor implements the Alpha instruction set and features 8-wide superscalar issue and simultaneous multithreading in a 0.125/spl mu/m SOI process. Performance is estimated at over three times that of the previous design.