Design of a direct digital synthesizer with an on-chip D/A-converter
Jouko Vankka, M. Waltari, Marko Kosunen, Kari A. I. Halonen · 2002
A Direct Digital Synthesizer (DDS) with an on-chip D/A-converter is designed and processed in 0.8 µm BiCMOS. The digital parts of the chip are implemented with CMOS design to reduce power consumption. The 10-bit D/A-converter is designed with BiCMOS technology in order to operate at a clock rate of 150 MHz. At the 150 MHz clock frequency, the Spurious Free Dynamic Range (SFDR) is 60 dBc at low synthesized frequencies, decreasing to 52 dBc at high synthesized frequencies in the output frequency band (0 to 60 MHz). The DDS covers the output frequency band in steps of 0.0349 Hz with the frequency switching speed of 140 ns. The chip has a complexity of 19,100 transistors with a die/core area of 12.2/3.9 mm2. The power dissipation is 0.6W at 150MHz @ 5V. The maximum operating clock frequency of the chip is 170 MHz.