Power savings in embedded processors through decode filter cache
Weiyu Tang, Rajesh K. Gupta, Alex Nicolau · 2002
Abstract In embedded processors, instruction fetch and decodecan consume more than 40 % of processor power. An instruction filter cache can be placed between the CPU coreand the instruction cache to service the instruction stream. Power savings in instruction fetch result from accesses to asmall cache. In this paper, we introduce decode filter cache to provide decoded instruction stream. On a hit in the de-code filter cache, fetching from the instruction cache and the subsequent decoding is eliminated, which results in powersavings in both instruction fetch and instruction decode. We propose to classify instructions into cacheable oruncacheable depending on the decoded width. Then sectored cache design is used in the decode filter cache so thatcacheable and uncacheable instructions can coexist in a decode filter cache sector. Finally, a prediction mechanismis presented to reduce the decode filter cache miss penalty. Experimental results show average 34 % processor powerreduction and less than 1 % performance degradation. 1.