Performance analysis of scheduling disciplines in hardware
Padmini Vellore, Ramachandran Venkatesan · 2004
Due to the availability of high bandwidth resulting from high capacity links, the packets can be transmitted through the link at great speeds. Therefore, the switch has to be fast enough to be able to switch packets from several incoming links into one outgoing link at a speed that matches the available link speed. The recent developments in the ASIC design have led to the hardware realization of certain scheduling algorithms (J.C.R. Bennett et al, Proc. IEEE/ICNP, pp. 7-14, 1997). These implementations try to reduce the complexity involved in realizing the algorithms in hardware so that they can be used in high-speed networks without causing considerable delay to the packets traveling through the switch. WFQ is one of the earliest scheduling algorithms proposed to approximate GPS, which is an idealized scheduling algorithm. WF/sup 2/Q+ is an improvement over WFQ which more closely approximates GPS and is less complex to implement (when compared with WFQ). It has been shown that WF/sup 2/Q+ does not always outperform WFQ for real-time sources (P. Vellore and R. Venkatesan, IEEE Newfoundland Electrical and Computer Eng. Conf., 2002). In this paper, we show the hardware implementation of both WFQ and WF/sup 2/Q+ and estimate the differences in the complexities involved in implementing the two algorithms in hardware.