Bus pumping at Gbits/s rate on MCM
T.-C. Lo, George A. Katopis, Michael Mcallister, C. K. Vakirtzis, Dale Becker · 2002
The roadmaps of high-end server performance strongly suggest that 1 GHz processors will be a reality early in the next century. This trend creates the requirement of a commensurate increase of the speed of the off chip interconnects so that the bus bandwidth between the processor and the L2 cache chips can be maintained without an explosion of the chip I/Os. However, this increase in interconnect speed can not be achieved by decreasing the physical distance between the chips because the number of processors in an SMP system keeps increasing (Mak, 1997). It follows that data storage on the transmission line is the only way to satisfy these diverse requirements. This technique has been used successfully in the past by IBM bipolar mainframes but at much lower operating frequencies and on FR4 board lines which have much smaller resistance than the transmission lines embedded in polyimide (thin film) or even those embedded in glass ceramic. Therefore, we have designed the experiment that this paper describes in order to establish the feasibility of 1 Gbit/s transmission rate on glass ceramic and thin film lines and verify the validity of our simulation models in this frequency range.