Testability features of a 32 kbps ADPCM transcoder
L.A. Bonet · 2003
Motorola's MC 145532 ADPCM (adaptive digital pulse-code-modulation) transcoder described is a 16-pin CMOS VLSI application specific digital signal processor (DSP) that implements in full-duplex mode the ANSI (T1.301-1987) standard algorithm for 32-kb/s ADPCM. The application is illustrated of structured test techniques, such as scan path and signature analysis, which are used to enhance the testability of this VLSI signal processor. To perform in real time the numerous computations required by the algorithm, the MC 145532 contains a DSP engine that executes microcode instructions at a 10 MHz rate. The MC145532 was built using 1.5- mu m CMOS technology that has double-level metal capability. The size is roughly 145*210 mils with a transistor count of approximately 50 k transistors.>