Automatic Test Plan Generation for Analog Integrated Circuits - A Practical Approach
R. Naiknaware, Ganeshram Nandakumar, Rajeev Arora, J. Larkin · 2005
This paper introduces a novel technique to generate Test Plans automatically for analog and mixed signal integrated circuits (ICs), which are designed using modulur design concept similar to tlwt of digital integrated circuits. Each block in tlie design will have a high level but accurate behaviorul model. These high level models are created during rhe design of the complete chip, and are also used for the simulation of the complete device. Given the design database of a chip, designed using these blocks, the proposed algorithm generates testplan for all the blocks of the chip. First the Test Values are set on the block to be tested. which may or may not be directly accessible from the design IOs of the IC. The algorithm tries tofinda consistent set of values to be set ut the design IOs, preserving the test values set on the internal block under test. Testplan generated consists, the values to be set and measuredat the design IOs of theIC, for carrying out the tests on that block. Implementation of this algorithm is presented with examples and results.