A pipelined divider with a small lookup table
Chin‐Long Wey, Shin-Yo Lin, Muh‐Tian Shiue · 2007
Abstract:- The design of fast dividers is an important issue in high speed computing because division account for a significant fraction of the total arithmetic operation. Taylor series expansion is a well-known multiplicative scheme for high-performance division implementation. This study presents a simple architecture that implements a pipelined divider including the first 6 terms of the Taylor series expansion for approximation. Results show that the developed pipelined divider takes a lookup table of 32B for single precision with a latency of 8.90ns, and 56KB for double precision with 11.46ns, where the circuit is synthesized with TSMC 0.18µm digital CMOS standard cell library.