Chip Partitioning Aid: A Design Technique for Partitionability and Testability in VLSI
Sumit DasGupta, Matthew Graf, R. A. Rasmussen, Ron Walther, T.W. Williams · 1984
This paper presents a structured partitioning technique which can be integrated into the design of a chip. It breaks the pattern of exponential growth in test pattern generation cost as a function of the number of chips in a package. In one of its forms, it also holds the promise of parallel chip testing, as well as migration of chip-level tests for testing at higher package levels.