A logic-to-logic comparator for VLSI layout verification
Peter Michael Maurer, A.D. Schapira · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1988
The logic-to-logic comparator (LLC) is described as a tool that verifies VLSI layouts by comparing the logic diagrams for a circuit with structures extracted from the circuit's layout. LLC can operate at either the gate or the transistor level, although the gate level is preferred. It is similar to other graph-isomorphism-based tools, but incorporates some important improvements. The most important of these is a path-comparison algorithm that uses dynamically calculated global information. In addition, LLC contains a gate-matching algorithm that can use certain types of symmetry to distinguish between gates that appear to be identical to less sophisticated algorithms. LLC has been used to verify several commercially available VLSI chips.>